Major Projects

Algorithmic Aspects of Hardware Software Partitioning

The aim is to develop optimal and computationally efficient algorithmic approaches to the problem of Hardware Software Partitioning so as to implement a system on two smaller sub-systems: hardware and software units. Application specific hardware can guarantee faster runtime than software, but is significantly more expensive. On the other hand, software is cheaper and generic but has higher time of execution. Thus, we implement performance critical components on hardware and other non-critical ones on software. This enables efficient use of resources available, reduces power consumption and accelerates the execution time of the embedded system. The project involves modelling the problem as a multi-objective optimization problem and then deriving pareto-optimal solutions to the same.

Guide: Dr Shubhajit Roy Chowdhury

Status: Ongoing

Publications:


  1. GMA : A High Speed Metaheuristic Algorithmic Approach to Hardware Software Partitioning for Low-cost SoCs, Naman Govil and Shubhajit Roy Chowdhury. At the 26th IEEE International Symposium on Rapid System Prototyping (IEEE RSP 2015), October 2015, Amsterdam. (Full Paper)
  2. High performance and low cost implementation of Fast Fourier Transform algorithm based on Hardware Software co- design, Naman Govil and Shubhajit Roy Chowdhury.At the IEEE Tensymp, April 2014, Kuala Lumpur. (Full Paper)

Data Access Methods for ARM SoCs

This project was done as a part of the Google Summer of Code (GSoC). The Project aim was to optimize and enhance the CBFS_media interface used for accessing data and in turn booting on low-end ARM SoCs. An ARM-specific CBFS Access pattern would enable coreboot to load its stages, which will form the basis for establishing full support for coreboot on ARM SoCs, and in-turn help bridge the gap between coreboot and ARM mainboards. The goal was to optimize the access patterns to CBFS_media (from any source) so that cache size is reduced considerably.

Guide: Aaron Durbin

Status: Completed

marketing

Radiation Tolerant FPGA Architectures

As a research intern under the Mitacs Globalink program at the Ecole Poly technique de Montreal, I worked on developing a novel space grade computing platform based on FPGAs. The first aim of the project was port the open-source RISC-V processor (Rocket Chip) to a non ARM core based FPGA (Stratix V). This involved using a soft core NIOS II processor on the Stratix V and altering the RISC-V front-end server to make it run on the Stratix V. Next, I worked on integrating a Xilinx SEM (Soft Error Mitigation) core IP to a Xilinx Zynq FPGA (Zedboard), for the purpose of fault insertion and scrubbing.

Guide: Dr Giovanni Beltrame

Status: Completed

marketing

Semantic Segmentation

As the course project for "Computer Vision", I worked on the problem of Semantic Segmentation, primarily foreground-background segmentation. The aim of the project was to perform semantic segmentation on the MSRC Dataset using MRF Energy functions. An SVM classifier was used to label the images and the results were further improved by employing alpha expansion to minimize the energy. For every image in the data, a graph consisting of the image pixels as the nodes was created. The weight of the edges between the nodes formed the pair-wise costs while the weight of the nodes with the terminal nodes (source and sink) formed the unary cost. The project was implemented using OpenCV libraries.

Guide: Dr C.V. Jawahar

Status: Completed

marketing

MessE

MessE provides students with a mobile platform to manage and plan their meal subscriptions and cancel meals that they will not use. This data is made available to the Hostel Food Manager who can then cook accordingly and avoid wastage. The system also provides for coordinated collaboration between messes and NGOs to get the left-over food to the needy. This is a system ideated and developed at a week long workshop organized by MIT Media Labs.

Guide: Amy Canham

Status: Completed

marketing

Texture Synthesis using Graph Cuts

Texture Synthesis is the process of patching regions from a sample image or a video and copied to the output so that they are stitched together along optimal seams to generate a new and typically larger output. I conducted a study of the novel methods in texture synthesis, based on the work of Graphcut Textures : Image and Video Synthesis Using Graph Cuts.

Guide: Dr C.V. Jawahar

Status: Completed

marketing

Missile Interface Unit

This project consisted of developing testing and debugging algorithms for testing all major modules of the On Board Chip (OBC), such as the CPLD, Bus Module (1553B), etc. This project was done under the guidance of Defence Research and Development Laboratory, Hyderabad (DRDL) which is a part of the Defence Research and Development Organisation(DRDO), Ministry of Defence, Govt of India.

Guide: DRDL,Hyderabad

Status: Completed

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Audio Visual Learning System

The aim of the project is to implement an Audio Visual Learning System for Kids. The system is to be implemented using Hardware/Software Co-Design on Digilent Nexys 2 board using Xilinx ISE tool. Alphabets A to Z and numbers 0 to 9 entered through keyboard shall be displayed over the VGA display, at the same time audio corresponding to the key being pressed shall be played on a speaker. The system shall be implemented in both hardware and software. VHDL shall be used as hardware description language and C as software.

Guide: Dr Shubhajit Roy Chowdhury

Status: Completed

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"Awaaz Do"

A sound triangulation device which tracks the speaker and remains directed towards him while he speaks. Once the speaker has completed, the device begins scanning the sample space for the next speaker and directs itself towards him. In a video conference set-up such a system enables better communication by directing the microphone towards the current speaker. The next-level implementation could be to miniaturise the system and attach it to a collar mic. This could solve the problem of inefficiency of collar mics.

Guide: Dr Jayanthi Sivaswamy

Status: Completed

marketing

Camera Caliberation

Camera Calibration is primarily the procedure of finding the quantities internal to the camera that affect the imaging process. It is needed when we need to reconstruct the world model, or interact with the world. Given image-world point correspondaces, found out the internal and external parameters such as rotation, translation, etc of the camera.

Guide: Dr C.V Jawahar

Status: Completed

marketing

ADC_2.0

In this project I designed my own ADC(Analog to Digital Converter) which was based on a SAR-based design but which does the conversion in N/2 clock cycles (where N is the number of bits). The design achieves a trade-off between speed (faster than SAR) and hardware consumption (lesser hardware requirements than a flash-ADC).

Guide: Dr Madhav Krishna

Status: Completed

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Speed Regulation and Control System

This is an electronics automated system which has the ability to detect the speed of moving vehicles and check whether they are with-in the speed limit. The prototype uses two LDR and lazer pairs at two distinct points. When the vehicle passes between them an interrupt is generated which is used for further decision making.

Guide: Vinay Kumar Mittal

Status: Completed

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Autonomous GMV

An Autonomous Ground Motor Vehicle which is capable of height detection and can avoid falls from the top of a table,etc. Once switched on it can traverse the whole table without falling down, intelligently avoiding edges and deciding paths to avoid a collision.

Guide: Vinay Kumar Mittal

Status: Completed

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Color Tracker

This is a color tracking bot which follows a certain color (programmable), built using Digital Image Processing on MATLAB and simple microcontroller programming.

Guide: Dr Madhav Krishna

Status: Completed

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